[LoongArch] Add patterns for vstelm instructions #139201
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@llvm/pr-subscribers-backend-loongarch Author: None (tangaac) ChangesFull diff: https://github.com/llvm/llvm-project/pull/139201.diff 2 Files Affected:
diff --git a/llvm/lib/Target/LoongArch/LoongArchLASXInstrInfo.td b/llvm/lib/Target/LoongArch/LoongArchLASXInstrInfo.td
index fe08c1050b4d7..802fd082564e1 100644
--- a/llvm/lib/Target/LoongArch/LoongArchLASXInstrInfo.td
+++ b/llvm/lib/Target/LoongArch/LoongArchLASXInstrInfo.td
@@ -1756,6 +1756,14 @@ def : Pat<(lasxsplatf32 FPR32:$fj),
def : Pat<(lasxsplatf64 FPR64:$fj),
(XVREPLVE0_D (SUBREG_TO_REG (i64 0), FPR64:$fj, sub_64))>;
+// VSTELM
+defm : VstelmPat<truncstorei8, v32i8, XVSTELM_B, simm12_addlike, uimm5>;
+defm : VstelmPat<truncstorei16, v16i16, XVSTELM_H, simm11_lsl1, uimm4>;
+defm : VstelmPat<truncstorei32, v8i32, XVSTELM_W, simm10_lsl2, uimm3>;
+defm : VstelmPat<store, v4i64, XVSTELM_D, simm9_lsl3, uimm2>;
+defm : VstelmPat<store, v8f32, XVSTELM_W, simm10_lsl2, uimm3, f32>;
+defm : VstelmPat<store, v4f64, XVSTELM_D, simm9_lsl3, uimm2, f64>;
+
// Loads/Stores
foreach vt = [v32i8, v16i16, v8i32, v4i64, v8f32, v4f64] in {
defm : LdPat<load, XVLD, vt>;
diff --git a/llvm/lib/Target/LoongArch/LoongArchLSXInstrInfo.td b/llvm/lib/Target/LoongArch/LoongArchLSXInstrInfo.td
index 1ffc5f8056b96..69fbf5ae45603 100644
--- a/llvm/lib/Target/LoongArch/LoongArchLSXInstrInfo.td
+++ b/llvm/lib/Target/LoongArch/LoongArchLSXInstrInfo.td
@@ -1446,6 +1446,20 @@ multiclass VldreplPat<ValueType vt, LAInst Inst, Operand ImmOpnd> {
(Inst BaseAddr:$rj, ImmOpnd:$imm)>;
}
+multiclass VstelmPat<PatFrag StoreOp, ValueType vt, LAInst Inst,
+ Operand ImmOpnd, Operand IdxOpnd, ValueType elt = i64> {
+ def : Pat<(StoreOp(elt(vector_extract vt:$vd, IdxOpnd:$idx)), BaseAddr:$rj),
+ (Inst vt:$vd, BaseAddr:$rj, 0, IdxOpnd:$idx)>;
+
+ def : Pat<(StoreOp(elt(vector_extract vt:$vd, IdxOpnd:$idx)),
+ (AddrConstant GPR:$rj, ImmOpnd:$imm)),
+ (Inst vt:$vd, GPR:$rj, ImmOpnd:$imm, IdxOpnd:$idx)>;
+
+ def : Pat<(StoreOp(elt(vector_extract vt:$vd, IdxOpnd:$idx)),
+ (AddLike BaseAddr:$rj, ImmOpnd:$imm)),
+ (Inst vt:$vd, BaseAddr:$rj, ImmOpnd:$imm, IdxOpnd:$idx)>;
+}
+
let Predicates = [HasExtLSX] in {
// VADD_{B/H/W/D}
@@ -1935,6 +1949,13 @@ def : Pat<(lsxsplatf32 FPR32:$fj),
def : Pat<(lsxsplatf64 FPR64:$fj),
(VREPLVEI_D (SUBREG_TO_REG (i64 0), FPR64:$fj, sub_64), 0)>;
+defm : VstelmPat<truncstorei8, v16i8, VSTELM_B, simm12_addlike, uimm4>;
+defm : VstelmPat<truncstorei16, v8i16, VSTELM_H, simm11_lsl1, uimm3>;
+defm : VstelmPat<truncstorei32, v4i32, VSTELM_W, simm10_lsl2, uimm2>;
+defm : VstelmPat<store, v2i64, VSTELM_D, simm9_lsl3, uimm1>;
+defm : VstelmPat<store, v4f32, VSTELM_W, simm10_lsl2, uimm2, f32>;
+defm : VstelmPat<store, v2f64, VSTELM_D, simm9_lsl3, uimm1, f64>;
+
// Loads/Stores
foreach vt = [v16i8, v8i16, v4i32, v2i64, v4f32, v2f64] in {
defm : LdPat<load, VLD, vt>;
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Files optimized. |
heiher
requested changes
May 13, 2025
heiher
approved these changes
May 15, 2025
SixWeining
reviewed
May 15, 2025
heiher
reviewed
May 16, 2025
Collaborator
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LLVM Buildbot has detected a new failure on builder Full details are available at: https://lab.llvm.org/buildbot/#/builders/174/builds/18095 Here is the relevant piece of the build log for the reference |
Contributor
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This change causes SPEC2017 521.wrf_r fails to build with A reduced llvm ir is attached. |
tru
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to llvmbot/llvm-project
that referenced
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Jul 24, 2025
…lvm#146455) This patch adds an emergency spill slot when ran out of registers. PR llvm#139201 introduces `vstelm` instructions with only 8-bit imm offset, it causes no spill slot to store the spill registers. (cherry picked from commit 64a0478)
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